1. Field of the Invention
The present invention relates to a circuit for compensating for the nonlinear distortion of a transmit power amplifier in a digital DC/AC modulating system.
2. Description of the Related Art
In the accompanying drawings, FIG. 3 Shows a distortion compensating unit as described in Japanese Patent Laid-Open No. Sho 61-214843. The distortion compensating unit comprises an input terminal 1 for receiving a sequence of transmit bits 10, a clock terminal 3 for receiving sample clocks 21, a mapping circuit 100 for generating symbol codes 20a and 20b from the sequence of transmit bits 10, a wave-form shaping filter 200 including a read-only memory used to generate sampled values 30a and 30b from the symbol codes 20a and 20b, a power amplifier 400, a distortion compensating circuit 300 for compensating for a distortion produced when the power amplifier 400 operates, a coupler 401 for taking out part of the output of the power amplifier 400 and an attenuator 402 for attenuating the signal taken out by the coupler 401.
The waveform shaping filter 200 comprises a frequency divider 210 for dividing sample clocks 21 by 2.sup.N (where N is an integer) to form symbol clocks 22, a 2.sup.N counter 211 for performing the counting operation on the sample clocks 21, a shift register 212 responsive to the symbol clocks 22, and a read-only memory 213 being addressed by the counts of the counter 211 and the contents of the shift register 212 to output the sampled values 30a and 30b therefrom.
The distortion compensating circuit 300 comprises a rewritable memory 310 for receiving read addresses from the sampled values 30a and 30b and for outputting a distortion compensation value used to compensate for a distortion produced when the power amplifier operates, an adder for adding the distortion compensation value from the memory 310 to the sampled values 30a and 30b, a digital/analog (D/A) converter 312 for converting a digital value from the adder 311 into an analog value, an oscillator 313 for generating carrier waves, a quadrature modulator 314 for modulating the carrier waves from the oscillator 313 by the output of the D/A converter 312, a quadrature demodulator 315 for demodulating part of the output taken from the power amplifier 400 by the coupler 401, an analog/digital (A/D) converter 316 for converting the analog output of the quadrature demodulator 315 into a digital value, a subtractor 317 for subtracting the digital output of the A/D converter 316 from the sampled values 30a and 30b, a correction factor generator 318 for computing a correction factor for the contents of the rewritable memory 310 from the output of the subtractor. 317, and a computing circuit 319 for performing the addition or subtraction between the outputs of the correction factor generator 318 and rewritable memory 310 and for suitably rewriting the contents of the rewritable memory 310 by the use of a value resulting from said addition or subtraction.
On operation, sampling clocks 21 inputted through the clock terminal 3 are 2.sup.N divided by the divider 210 into symbol clocks 22 which in turn drive the shift register 212 to shift the symbol codes 20a and 20b from the mapping circuit 100. In such a manner, the sampled values 30a and 30b will be read out from the read-only memory 213.
The operation of the distortion compensating circuit 300 will now be described.
For each sampled value, part of the output of the power amplifier 400 is taken out and demodulated to take a difference between the demodulated value and that sampled value, which difference is used to detect a distortion produced by the power amplifier 400. On detection, the distortion is stored in the memory 310 corresponding to the transmitted sampled value. When the same sampled value again appears on the base band signal 31a and 31b, the distortion produced by the power amplifier 400 can be negated by the distortion compensating circuit 300 if a distortion equivalent to that produced by the power amplifier 400 has already been applied to the sampled value. This can be accomplished by reading the distortion value corresponding to that sampled value which has been stored in the memory 310 and adding the distortion value to the sampled value.
In the distortion compensating unit shown in FIG. 3, the rewritable memory 310 has previously stored distortion components to be added to the sampled values 30a and 30b to compensate for the distortion produced by the nonlinearity in the power amplifier 400. First of all, distortion compensating factors corresponding to the sampled values 30a and 30b are read out from the rewritable memory 310 using these sampled values 30a and 30b as addresses. The first adder 311 adds the sampled values 30a and 30b to the output of the rewritable memory 310 to obtain base band signals 31a and 31b compensated in distortion. These base band signals 31a and 31b are then converted into analog signals by the D/A converter 312. The quadrature modulator 314 uses the analog signals to modulate the carrier waves 313. The modulated carrier waves 313 are amplified by the power amplifier 400, the output of which is partially taken out by the coupler 401. The taken-out signals are attenuated to an appropriate level by the attenuator 402 and then demodulated into base band signals by the quadrature demodulator 315. These base band signals are converted into digital values by the A/D converter 316. The subtractor 317 subtracts the digital values from the sampled values 30a and 30b which should correctly be transmitted. If the rewritable memory 310 has outputted a distortion compensation factor sufficient to negate the nonlinear distortion in the power amplifier 400, the output of the subtractor 317 will be zero. The correction factor generator 318 increases the output of the subtractor 317 by .alpha. times (0&lt;.alpha..ltoreq.1), which is in turn added to the output of the rewritable memory 310 at the computing circuit 319. The resulting value is again written into the memory. In such a manner, the distortion to be compensated for will suitably be controlled and rewritten in the rewritable memory 310.
Since the distortion compensation values have been written in the memory at the storage areas corresponding to the base band data in the distortion compensating unit of the prior art as described, it is required to rewrite all the data in the memory to converge the distortion compensation value into an appropriate value. Therefore, the proper distortion compensation requires a given time period.